CS&E, ECE team up to win IEEE ICLAD Best Paper Award

Department of Computer Science & Engineering (CS&E) associate professor Caiwen Ding was the last author of the paper that won the 2025 IEEE International Conference on LLM-Aided Design (ICLAD) Best Paper Award. The paper titled, “HiVeGen - Hierarchical LLM-based Verilog Generation for Scalable Chip Design,” was a joint effort between CS&E and the Department of Electrical and Computer Engineering (ECE). PhD students Jinwei Tang (CS&E) and Jiayin Qin (ECE) were the primary authors on the paper exploring how Large Language Models (LLMs) can improve the chip design process. 

“This is a great collaboration match for CS&E and ECE,” Ding said. “The computer scientists focus on developing the machine learning models and customizing LLMs to work for chip design. ECE researchers analyze and incorporate the hardware constraints to make sure that the LLMs generate good designs.”

HiVeGen is a framework designed to scale up Verilog generation using LLMs by breaking down the process into hierarchical submodules that align with LLM capabilities. It enhances this approach by integrating automatic Design Space Exploration (DSE) into hierarchy-aware prompt generation, employing weight-based retrieval to encourage code module reuse.

Traditional LLM-based methods face difficulties handling complex designs, resulting in incomplete outputs and lower code quality. Additionally, manual DSE is costly and time-consuming, especially for intricate hardware architectures. HiVeGen achieves up to 30.97% token savings and 45.24% reduction in generation time on average compared to using LLM only-based generation, while improving accuracy.

“We are working on a user-friendly chip design process,” Ding said. “It can take trained experts weeks, even months, to come up with a fairly large chip design. Now using large language models, we can significantly speed up this design process. However, this is not a trivial task. There are a number of obstacles that we have to overcome and that is what our paper talks about.”

In addition to Ding, Tang, and Qin, CS&E’s assistant professor Zhu-Tian Chen and ECE’s Louis John Schnell Professor Yu (Kevin) Cao and assistant professor Yang (Katie) Zhao are also involved with the project. 

“Zhu-Tian has also contributed a valuable human-computer interaction perspective. His work involves incrementally generating the Verilog code draft through an on-the-fly parser as the user types a prompt, before invoking the LLMs. This approach helps make the LLM’s behavior more predictable.”

After presenting their work at the IEEE ICLAD conference at Stanford University to a crowd of over 350 people, the project has garnered interest from peer institutions around the world, as well as industry leaders in chip manufacturing. 

“I really want to highlight our outstanding students. They formed an excellent partnership on this project. Following this best paper award, they have had another paper accepted at another prestigious conference, 2025 ICCAD. Jinwei and Jiayin are both just first year PhD students and have already contributed to two important publications. I feel very fortunate to have the opportunity to work with them as a team.”

Learn more and check out the full paper.