Professor Keshab Parhi named ACM Fellow
Parhi is a professor in the Department of Electrical and Computer Engineering, and is also a member of the data science graduate faculty. He is a leader in design techniques and tools that enable hardware accelerators for digital signal processing (DSP) and networking systems, and is well known across the world for his contributions to hardware accelerators, the key building blocks of computing systems. Parhi’s research outcomes have advanced achievable data rates (that would otherwise only have evolved over several technology generations), and made chips more energy and cost efficient. The Gigabit Ethernet chip that has been in use in computers since 1998 is a result of his accelerator designs. Parhi holds 31 US patents, and has authored 650 papers, and his inventions and research have benefited many companies: Broadcom, Marvell, Aquantia, Qualcomm, Samsung, Texas Instruments (TI), and Intel are some of them. In 2003, he was awarded the IEEE Kiyo Tomiyasu Technical Field Award for his groundbreaking contributions to broadband communications systems. In the light of the communication industry’s search for faster and energy efficient technologies as conventional silicon CMOS technologies slow down, Parhi’s work has gained further significance and impact.
Speeding up the Internet
Physical layer communications transceiver chips are the backbone of both, wired and wireless internet. The DSP functions and error-control coders in these transceivers contain many layers of feedback loops, and the computation demands cannot be achieved using traditional pipelining and/or parallel processing. Keshab’s research on algorithm-architecture transformations has overcome these bottlenecks and has paved the way for a faster wired and wireless internet.
A pioneer of many forms of look ahead approaches for pipelining and parallel processing in DSP computations, Parhi proposed the pipelining of quantizer loops, using parallel-branch delayed decision. This was particularly critical to companies such as Broadcom, Lucent, and Marvell for the development of the Gigabit Ethernet chip. Parhi’s pioneering and innovative spirit were on display during a stint at Broadcom. When the company struggled to meet the throughput requirements of serializers/deserializers and backplanes for data rates in excess of 10 Gbps, he created arbitrarily-parallel decision-feedback equalizers where the chip complexity grew logarithmically with respect to the level of parallelism, Later, when the linear feedback shift register in Broadcom’s fiber transceiver could not be operated at the 10 Gbps data rate due to the fanout bottleneck, he developed a new parallel linear feedback shift register architecture.
Parhi’s high-speed parallel architecture design of the Tomlinson-Harashima precoder was instrumental in the creation and preservation of the IEEE 802.3an standard for 10-gigabit Ethernet on copper. His fast parallel filters with sub-linear complexity were critical to overcome the excessive costs and energy consumed for data transmission at 10 to 400 Gbps.
His work on parallel decoders is at the vanguard of modern error-control codes that approach the Shannon limit, and his low-latency polar code decoder architectures are in use in 5G smartphones.
Tools for accelerator design
Professor Keshab Parhi’s ground-breaking papers on high-level transformations on iterative data-flow graphs (DFGs) include systematic unfolding and folding. Digital filters designed using folding have been deployed in cable modems, set-top boxes and radio-frequency demodulators by companies such as Broadcom, TI, and others. Parhi used folding transformation to develop FFT architectures that achieve full hardware utilization, do not contain feedback loops, and can be pipelined at arbitrary levels. These FFT architectures are incorporated into 5G iPhones.
With the aid of DARPA funding, Parhi developed the Minnesota architecture synthesis (MARS) high level DSP synthesis system. A powerful tool, it has paved the way for synthesis of chips from hardware descriptions to highly pipelined functional units while guaranteeing the fastest possible scheduling. Parhi’s other contributions include crypto-accelerators for RSA and AES for fast secure e-commerce transactions, fast and accurate power estimation (his paper on the topic was named the 1996 ACM/IEEE Design Automation Conference Best Paper, and the technology deployed in Synopsys PowerMill Tool), and obfuscation techniques for hardware security (2017 IEEE Transactions on Very Large Scale Integration Systems Best Paper Award).
Other awards and service
VLSI Digital-Signal-Processing Systems: Design and Implementation (Wiley, 1999), authored by Professor Keshab Parhi is considered an authoritative textbook, and is used by graduate students and practicing engineers across the world. The book won him the Frederick Emmons Terman award from the American Society for Engineering Education (ASEE). In his academic tenure so far, he has supervised 48 doctoral theses, 65 master’s theses, 19 visiting pre- and postdoctoral fellows, and numerous undergraduate senior design projects. His students are employed in technology companies, academic institutions, and government research laboratories, with several of them being IEEE Fellows.
Parhi is the recipient of several awards that recognize his brilliant contributions. The most recent awards include the Mac Van Valkenburg Award from IEEE CASS (2017), and Fellow of the American Association for the Advancement of Science (2017). In December 2020, the National Academy of Inventors announced that Professor Keshab Parhi was to be inducted Fellow of the National Academy of Inventors (NAI) in recognition of his “highly prolific spirit of innovation in creating or facilitating outstanding inventions that have made a tangible impact on the quality of life, economic development, and the welfare of society.” The Department of Electrical and Computer Engineering is proud of Professor Parhi’s achievements and congratulates him on his well-earned election as Fellow of the ACM.