Prof. Baris Taskin at the Wilson Lecture Series

Inter-Chiplet Synchronization of Multi-Die VLSI Systems

In VLSI systems, computing is projected to contain hundreds of components from heterogeneous processors, memories, and interconnect, in order to achieve performance gains and energy-efficiency in the face of increasing power-density. However, both hardware and software designers are faced with limitations in the improvement of instructions-per-cycle and clock frequency. As a result, designers have sought out heterogeneous computing devices, in system architecture and VLSI packaging, to accelerate current and future workloads.  At the VLSI packaging level, silicon interposer based heterogeneous integration of multi-die systems (MDS) has provided a new avenue for scaling of in-package computation, memory, and interconnects.

In this talk, I will focus on the synchronization subset of our efforts for silicon interposer based integration of VLSI multi-die systems (MDS).  In particular, I will present the solution our team has developed for inter-die synchronization in MDS that has a resonant clocking technology backbone. Resonant clocking technologies, which work on adiabatic, charge-recycling switching principles, generate very high frequency clock signals at a low power dissipation rate. In MDS, the presented implementation has a minimum footprint on the active interposer, which is important for yield and cost.  The proposed solution provides a centralized, synchronized and lightweight clock generation and delivery system that eliminates the need for PLLs and various clock/phase correction/synchronization overhead, which could especially be prohibitive for large scale MDS systems.  In addition to a superior synchronization profile, the proposed resonant clocking delivery leads to an average of ~40% total chiplet power savings (~72% on the clock network) in comparison to PLL-synchronized ARM Cortex M0-based 10mm by 12mm multi-core MDS simulation model.  At the end of this talk, I will also highlight two specific solutions our team developed for increased heterogeneity in architectures (and their efficiency) using resonant-clocking based inter-chipset synchronization,  where these architectures 1) demand frequency/voltage points distributed both spatially and temporally to achieve optimal performance, 2) require efficient I/O interface between chiplets.

About the speaker

Baris Taskin received the B.S. degree in electrical and electronics engineering from Middle East Technical University (METU), Ankara, Turkey, in 2000, and the M.S. and Ph.D. degrees in electrical engineering from University of Pittsburgh, Pittsburgh, PA, in 2003 and 2005, respectively. He joined the Electrical and Computer Engineering Department at Drexel University, Philadelphia, PA in 2005, where currently he is a Professor. Between 2003-2004, he was a PhD intern engineer at MultiGiG Inc., Scotts Valley, CA, working on electronic design automation of integrated circuit timing and clocking. He is an "A. Richard Newton Award" winner from the ACM SIGDA in 2007 (for junior faculty starting new programs in EDA), a recipient of the Faculty Early Career Development Award (CAREER) from the National Science Foundation (NSF) in 2009, the Distinguished Service Award from ACM SIGDA in 2012, the Young Electrical Engineer of the Year Award from IEEE Philadelphia in 2013 and the Drexel ECE Department's Outstanding Research Award in 2015. He is an associate editor for JCSC and Elsevier's Microelectronics. He served as the General Chair for SLIP 2016 and GLVLSI 2019, as the Chair for IEEE CEDA Pennsylvania Chapter (2018-current), and the Chair of the IEEE Circuits and Systems Society's VLSI and Systems Applications Technical Committee (IEEE CASS VSA-TC) (2018-2020). Learn more about Drexel University's VLSI and Architecture Laboratory (VANDAL).


Start date
Thursday, Jan. 27, 2022, 4 p.m.
End date
Thursday, Jan. 27, 2022, 5 p.m.