Paper on HiVeGen a new framework for scaling up Verilog generation wins IEEE ICLAD award
The 2025 IEEE International Conference on LLM-Aided Design (ICLAD) Best Paper Award has been conferred on a joint team of researchers led by Professors Yang Zhao, Yu Cao (both ECE), Caiwen Ding, and Zhu-Tian Chen (both Department of Computer Science and Engineering). The team’s paper is titled, “HiVeGen - Hierarchical LLM-based Verilog Generation for Scalable Chip Design.”
Large language models (LLMs) have demonstrated their effectiveness in generating code which has encouraged researchers to extend their capacity to hardware description language (HDL). However LLMs present specific challenges when used to generate HDL code. Traditional LLM-based methods struggle to handle complex designs which results in incomplete outputs or lower code quality. Additionally, manual Design Space Exploration (DSE) is a costly and time-consuming endeavor, especially for complex hardware architectures, making it an unsuitable fix for the inadequacies of traditional LLMs.
HiVeGen, the team’s answer to these challenges, is a framework designed to scale up Verilog generation using LLMs by breaking down the process into hierarchical submodules that align with LLM capabilities. HiVeGen’s approach is enhanced by integrating automatic Design Space Exploration (DSE) into hierarchy-aware prompt generation, employing weight-based retrieval to encourage code reuse. It has shown token savings over 30 percent and a 45 percent reduction in generation time on average as compared to using LLM only-based generation, while improving accuracy. Also, HiVeGen supports power, performance, area (PPA)-aware generation which enhances the quality of Verilog designs.
The other authors of the paper are Jinwei Tang, Kiran Thorat, and Jiayin Qin. Thorat is a student at the University of Connecticut working under the supervision of Professor Caiwen Ding who was previously faculty there.
The 2025 IEEE International Conference on LLM-Aided Design centers on leveraging Large Language Model (LLM) technology to enhance the design of circuits, software, and computing systems by improving quality, productivity, robustness, and cost-efficiency. As the first international conference dedicated exclusively to this emerging field, it aims to highlight cutting-edge research that harnesses generative AI advances and introduces innovative methods and solutions for design automation, software development, and related areas. The event features leading researchers, showcases open-source LLM models, datasets, and tool flows, and offers benchmarking, testing, and validation techniques. Learn more about the conference.
This year, the conference saw a surge in interest with 108 submissions (more than twice the number of submissions last year) of which 32 papers were accepted. The paper on HiVeGen was one of only two papers to be recognized with the best paper award. The conference attracted around 350 attendees from around the world.
Read “HiVeGen - Hierarchical LLM-based Verilog Generation for Scalable Chip Design.”