Professor Sachin Sapatnekar receives 2026 ACM/SIGDA Pioneering Achievement Award
Award recognizes Sapatnekar's groundbreaking contributions to EDA that have significantly advanced the ability to design high-performance integrated systems.
Professor Sachin Sapatnekar (Distinguished McKnight University Professor and Robert and Marjorie Henle Chair in ECE) was recently honored by the Association for Computing Machinery’s Special Interest Group on Design Automation (ACM/SIGDA) with the 2026 Pioneering Achievement Award.
ACM is the world's largest educational and scientific computing society and the award recognizes individuals for their outstanding contributions to electronic design automation (EDA) through publications, industrial products, or other impactful achievements over the course of their careers.
On hearing the news of the award, Sapatnekar said, “This came out of the blue: I didn't even know that I had been nominated. The list of past winners looks like an all-time who's-who list in EDA. I am truly honored to even be spoken of in the same sentence as them.”
Modern integrated circuits (ICs) contain billions of minute components, each with dimensions of just a few nanometers. Building such large systems manually is impossible. The task of EDA is to develop algorithms and software so that computers can automatically solve computationally difficult problems to facilitate IC design. EDA algorithms are thus vital in enabling circuit and system design engineers to manage the complexities of handling a gigantic number of components, while incorporating the intricacies of physics at the nanoscale.
Sapatnekar’s contributions in EDA have spanned areas ranging from digital to analog systems, from silicon-based approaches to new non-silicon technologies, and from contemporary to emerging computing paradigms. His work has been particularly influential in five key areas: digital circuit timing, analog circuit automation, physical design, power integrity, and circuit reliability. His research on timing analysis and optimization has had a significant impact. In particular, to determine the impact of manufacturing variations on circuit speed, he proposed efficient linear-time methods, improving over prior computationally intensive approaches that were impractical for commercial use. Ten years after publication, his work on timing variability was recognized by a test-of-time award* at the International Conference on Computer-Aided Design (ICCAD). For sequential circuit timing optimization, he developed a novel insight connecting clock skew optimization with retiming, leading to an efficient graph-theoretic solution that provided significant computational improvements over the prior state of the art.
Sapatnekar has also made groundbreaking contributions to IC physical design. In collaboration with industry researchers he introduced novel techniques for early planning of buffer and wire resources, greatly reducing congestion bottlenecks in prior methods. 3D IC design is an emerging technology that stacks circuitry in layers as chips run out of real estate: he has authored pioneering papers in this area on temperature-driven IC placement and thermal mitigation using appropriately placed thermal vias. For analog circuit layout, a problem that has defied EDA solutions for decades, he worked with Professor Ramesh Harjani (Edgar F. Johnson Professor in ECE), Professor Jiang Hu at Texas A&M University, and researchers at Intel Labs to build ALIGN (Analog Layout, Intelligently Generated from Netlists), which is arguably the most comprehensive solution to the problem to date. His work has resulted in open-source software tools and techniques that have been widely recognized and validated.
Sapatnekar has also developed solutions to critical challenges that affect power integrity and circuit reliability. Working with colleagues in industry, he proposed random-walk-based power grid analysis methods as well as hierarchical analysis methods, both of which overcame the challenges posed by the immense scale of on-chip power grids. His study of on-chip power grid optimization using decoupling capacitors is among the most frequently cited studies on the topic. He created analytical models for device reliability in integrated circuits, in collaboration with Professor Chris Kim (McKnight Presidential Endowed Chair, Distinguished McKnight University Professor in ECE), considering their impact from the device to the circuit to the system level; a related paper won a second ICCAD test-of-time award*. In the past few years, he has developed a suite of efficient linear-time analytical solutions for electromigration in on-chip wires, which causes wires to break as they age.
His current research interests are in harnessing machine learning methods for EDA, analyzing and optimizing heterogeneously integrated systems using advanced packaging technologies (with Louis John Schnell Professor Kevin Cao), automating analog/RF/mm-wave design from specification to layout, and Ising computation (with Professor Chris Kim and Jim and Sara Anderson Professor Ulya Karpuzcu).