High-Speed CMOS Silicon Photonic PAM4 Transceiver Front-End Circuits

Professor Samuel Palermo at ECE spring 2026 colloquium

Growing datacenter bandwidths datacenters requires optical transceivers operating at high data rates. Further increases in bandwidth density is possible with Wavelength-division multiplexing, which architectures based on silicon photonic microring modulators (MRMs) inherently enable. This talk covers high-speed PAM4 transmitter and receiver front-ends implemented in a 28nm CMOS process that are co-designed with these silicon photonic optical devices. The transmitter utilizes an optical DAC approach with two PAM2 AC-coupled pulsed-cascode high-swing output stages to drive the MRM MSB/LSB segments with a 3.42V ppd at 80Gb/s PAM4. The receiver consists of a transimpedance amplifier with sub-Nyquist bandwidth for low input-referred noise and a subsequent continuous-time linear equalizer for bandwidth recovery. Efficient clocking is realized with an LC-oscillator-based quarter-rate digital clock and data recovery system. The RX achieves 100Gb/s PAM4 operation with −6.4 dBm sensitivity.