Coupled-oscillator-based Ising chip COBI proves significantly superior in key benchmarking tests

ECE researchers led by Professor Ulya Karpuzcu successfully demonstrated a coupled-oscillator-based Ising (COBI) chip that can efficiently solve combinatorial optimization problems (COPs) in a significantly time and energy efficient manner as compared to both software algorithms and emerging quantum annealers. 

The details of the chip design, characterization, benchmarking results, and comparisons to alternatives are published in Nature Electronics, in a paper titled “A coupled-oscillator-based Ising chip for combinatorial optimization.” This is the second paper published in Nature Electronics that has emerged from the research supported by the DARPA Quantum-Inspired Classical Computing (QuICC) program grant. The grant was awarded in 2023 to McKnight Presidential Endowed Chair and Distinguished McKnight University Professor Chris Kim, one of the authors of the study. 

COPs are more commonly prevalent than we think. They exist in real-world situations in diverse applications that include machine learning, bioinformatics, robotics, drug discovery, scheduling and route optimization, chip design, and smart grid design. The goal in these diverse applications is to seek optimal solutions to complex problems. Existing Ising-based software and hardware approaches to solving large COPs of practical value present significant challenges. In the case of software solvers, such COPs become intractable while efficiency improvements in the case of hardware solvers (that operate in a manner similar to the software solvers) are marginal compared to the software alternatives. 

Array of COBI chips with a pencil lead in the frame for size reference
Array of COBI chips as they arrive from TSMC before they are packaged on to boards. The pencil head in the image is for size reference. Each die is 2.4mm x 2.0 mm.

The team addresses these limitations through their solution, COBI, a 59-spin all-to-all connected Ising machine with a new type of coupler circuit that only consumes switching power when two coupling signals interact with each other. The COBI chip is fabricated using off-the-shelf components using mature and therefore reliable technology in a standard semiconductor foundry, and it operates at room temperature. These features make it robust and capable of sidestepping any efficiency losses from an immature technology or a highly specialized operating environment. In addition to these unique features, a highlight of this chip is its topology: all-to-all connections with 59 nodes reduces overheads that might typically be involved in locally-connected architectures. 

Commenting on the significance of the study, the lead author Ulya Karpuzcu (Jim and Sara Anderson Professor in ECE) says, "Compared to the closest alternative CMOS-based Ising machine, our approach offers a higher number of all-to-all connected spins, and our novel coupling circuitry results in two orders of magnitude less energy consumption. We have demonstrated that as a result the COBI chip can solve representative COPs in a substantially more energy-efficient manner than optimized classical solvers in software and emerging quantum annealers. Due to its energy-efficiency and all-to-all connectivity, COBI can also efficiently solve dense COPs that cannot be solved by quantum annealers."

In benchmarking tests that the team ran against several existing classical software solvers and quantum annealers used for COPs, COBI has shown significant promise. The energy-to-solution was up to two orders of magnitude lower than the software solver and up to five orders of magnitude lower than the hardware/quantum annealer. The cryogenic cooling required for the quantum annealers accounts for their high energy-to-solution requirements as compared to COBI and software solvers included in the test. 

Referring to results of the benchmarking tests, Karpuzcu says, “This study shows that we can solve a diverse set of COPs representative of emerging real-world applications substantially more energy-efficiently than quantum computers without compromising the time to solution, using off-the-shelf electronic components.”

COBI’s design enables it to solve not only typical COPs but also those that are deemed intractable for present day quantum annealers. Looking ahead, scaling up the chip for deployment in real settings is the next challenge for the research team. 

Karpuzcu addresses the potential for scaling up: “Scaling to larger systems is possible by increasing the spin count per chip, and increasing the number of chips in the system. The first option is less effective from a practical perspective as we cannot increase the number of spins per chip indefinitely; the maximum number of spins per chip will be limited by fundamental physics. With the second option, however, a single Ising chip could potentially form a core computational building block in a larger scale system to solve emerging practical optimization problems. Our chip is a significant step towards larger scale Ising machines. The key question then is how to distribute the problem across multiple chips.”

In addition to Karpuzcu, the research team included Hüsrev Cılasun, William Moy, Ziqing Zeng, Tahmida Islam, Hao Lo, Alex Vanesse, Megan Tan, Mohammad Anees, Ramprasath S., Abhimanyu Kumar, and Professors Sachin S. Sapatnekar and Chris H. Kim, all from the Department of Electrical and Computer Engineering.

Read the full paper titled “A coupled-oscillator-based Ising chip for combinatorial optimization” published in Nature Electronics.

This work was supported by the Defense Advanced Research Projects Agency (DARPA) Quantum-Inspired Classical Computing (QuICC) programme under Air Force Research Laboratory (AFRL), National Science Foundation (NSF), Semiconductor Research Corporation, and Intel's Transformative HardWare for AI (THWAI) centre.

This is the second paper published in Nature Electronics on research supported by the DARPA Quantum-Inspired Classical Computing (QuICC) awarded to Professor Kim in early 2023. Read our news post on the first paper on the Ising solver chip

Other papers authored by the ECE research team on the Ising solver chip include:
3SAT on an all-to-all-connected CMOS Ising solver chip
DROID: discrete-time simulation for ring-oscillator-based Ising design
Both are published in Scientific Reports, a Nature journal

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