Microelectronics Co-design Research Group

My research leverages recent insights in computer engineering and semiconductor technology to tackle the challenge of microelectronics co-design for energy-efficient computing. Through integrated circuit design, physical analysis, and machine learning methods, our objective is to advance the frontier in computing hardware for future intelligent systems. Recent research initiatives include AI hardware acceleration, in-memory computing, cryogenic CMOS design, and 3D integration of heterogeneous chiplets.

Visit Yu [Kevin] Cao's Experts@Minnesota profile page

Education

Ph.D., Electrical Engineering and Computer Sciences, 2002, University of California, Berkeley, CA
M.A., Biophysics, 1999, University of California, Berkeley, CA
B.S., Physics, 1996, Peking University, China

Professional Background

Digital circuits and systems, microelectronics co-design, AI hardware, neural-inspired computing, reliable integration of emerging devices.

Teaching Subjects

• EE 5323 VLSI Design I
• EE 5324 VLSI Design II
• Special Topics on VLSI Design for Reliability

Honors and Awards

2022 Best IP Award, Design, Automation and Test in Europe Conference
2022 Distinguished Lecturer of the IEEE Circuits and Systems Society (CAS)
2020 Intel Outstanding Researcher Award
2017 IEEE Fellow
2012 Best Paper Award, IEEE Computer Society Annual Symposium on VLSI
2009 ACM SIGDA Outstanding New Faculty Award
2009 Promotion and Tenure Faculty Exemplar, Arizona State University
2009 Distinguished Lecturer of the IEEE Circuits and Systems Society (CAS)
2007 Best Paper Award, International Symposium on Low Power Electronics and Design
2007 IBM Faculty Award
2006 NSF Faculty Early Career Development (CAREER) Award
2006 IBM Faculty Award
2004 Best Paper Award, International Symposium on Quality Electronic Design

Selected Publications

G. R. Nair, H. Suh, M. M. Halappanavar, F. Liu, J. Seo, Y. Cao, “FPGA acceleration of GCN in light of the symmetry of graph adjacency matrix,” Design, Automation, and Test in Europe, 2023.

Z. Wang, G. R. Nair, G. Krishnan, S. K. Mandal, N. Cherian, J. Seo, C. Chakrabarti, U. Y. Ogras, Y. Cao, “AI computing in light of 2.5D interconnect roadmap: Big-little chiplets for in-memory acceleration,”
International Electron Devices Meeting, 2022.

G. Krishnan, Z. Wang, I. Yeo, L. Yang, J. Meng, M. Liehr, R. Joshi, N. C. Cady, D. Fan, J. Seo, Y. Cao, “Hybrid RRAM/SRAM in-memory computing for robust DNN acceleration,” IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 11, pp. 4241-4252, November 2022.

G. Krishnan, S. Mandal, M. Pannala, C. Chakrabarti, J. Seo, U. Ogras, Y. Cao, “SIAM: Chiplet-based scalable in-memory acceleration with mesh for deep neural networks,” ACM Transactions on Embedded
Computing Systems, vol. 20, no. 5s, pp. 1-24, October 2021.

Y. Cao, Predictive Technology Model for Robust Nanoelectronic Design, Springer, 2011 (http://dx.doi.org/10.1007/978-1-4614-0445-3).

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