Kia Bazargan
Photograph of Professor Kia Bazargan

Kia Bazargan

Associate Professor, Department of Electrical and Computer Engineering

Contact

612-625-4588
kia@umn.edu
Kenneth H. Keller Hall
Room 4-159
200 Union Street Se
Minneapolis, MN 55455

Education

Ph.D., 2000, Northwestern University, Evanston, IL, United States
M.S., 1998, Northwestern University, Evanston, IL, United States
B.S., CS, 1996, Sharif University of Technology, Tehran, Iran

Professional Background

Field-programmable gate arrays, Computer-aided design of VLSI circuits and systems

Research Interests


Bazargan Research Group Site ​​​​

My research interests are primarily in the field of VLSI-CAD. They include FPGA physical design, reconfigurable computing, and ASIC floorplanning/placement. I do some FPGA designs as well. In the past couple of years, I have focused on Stochastic Computing, which uses an analog-like encoding scheme: numbers are represented by streams of 1’s and 0’s. The ratio of 1’s to the length of the stream shows the value as a “probability”. Simple logic can perform complex operations on stochastic streams (e.g., an AND gate can multiply two probabilities).

Advances in the FPGA technology have made them increasingly more powerful in the past decade, and their market share is increasing every year. The main reason for their popularity is their flexibility in changing designs without having to go through more fabrication cycles. However, the performance, power, and area efficiency of FPGAs lags behind their ASIC counterparts. My objective is to bridge the gap between ASICs and FPGAs by devising better architectures, CAD algorithms, and programming paradigms.

Visit Kia Bazargan's Experts@Minnesota profile page.

Teaching Subjects
EE 5323 VLSI Design I
EE 5324 VLSI Design II
EE 5301 VLSI Design Automation I
EE 5302 VLSI Design Automation II
EE 2361 Introduction to Microcontrollers

Honors and Awards

National Science Foundation CAREER award, 2003

Books

Book Chapters

Sayed Abdolrasoul Faraji, M. Hassan Najafi, Bingzhe Li, Kia Bazargan and David Lilja, "Energy-Efficient Convolutional Neural Networks with Deterministic Bit-Stream", in Hardware Architectures for Deep Learning, Masoud Daneshtalab and Mehdi Modarressi, Institution of Engineering and Technology (IET), 2019.

Weikang Qian, Marc D. Riedel, Kia Bazargan, and David J. Lilja, "Synthesizing combinational logic to generate probabilities: theories and algorithms," in Advanced Techniques in Logic Synthesis, Optimizations and Applications, Sunil Khatri and Kanupriya Gulati editors, Springer Publishing, 2011.

Kia Bazargan, "Chapter 10.2: FPGA Technology Mapping, Placement, and Routing", in The Handbook of Algorithms for VLSI Physical Design Automation, Charles J. Alpert, Dinesh P. Mehta, and Sachin S. Sapatnekar, CRC Press

Sachin Sapatnekar, Kia Bazargan, "Chapter 10.4: 3D Design", in The Handbook of Algorithms for VLSI Physical Design Automation, Charles J. Alpert, Dinesh P. Mehta, and Sachin S. Sapatnekar, CRC Press.

Selected Publications

Soheil Mohajer, Zhiheng Wang, Kia Bazargan and Yuyang Li, “Parallel Unary Computing Based on Function Derivatives”, ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2020.

Zhiheng Wang, Devan Larson, Morgen Barker, Soheil Mohajer, and Kia Bazargan, "Deterministic Shuffling Networks to Implement Stochastic Circuits in Parallel", in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020, doi: 10.1109/TVLSI.2020.2984731

S. Rasoul Faraji and Kia Bazargan, "Hybrid Binary-Unary Hardware Accelerator", IEEE Transactions on Computers (TC), 2020.

M. H. Najafi, D. J. Lilja, M. Riedel, and K. Bazargan, "Low Cost Sorting Network Circuits using Unary Processing", TVLSI - IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 26, No. 8, pp. 1063-8210, 2018.

M. H. Najafi, Shiva Jamali-Zavareh, D. J. Lilja, M. D. Riedel, K. Bazargan, and R. Harjani, "An Overview of Time-based Computing with Stochastic Constructs," in IEEE Micro, 2017.

M. H. Najafi, D. J. Lilja, M. D. Riedel and K. Bazargan, "Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits," in IEEE Transactions on Computers, vol. 66, no. 10, pp. 1734-1746, Oct. 1 2017.[Selected as IEEE Transaction on Computers' Feature Paper of the Month]

M. Hassan Najafi, P. Li, D. J. Lilja, W. Qian, K. Bazargan, M. Riedel, "A Reconfigurable Architecture with Sequential Logic-based Stochastic Computing," ACM Journal on Emerging Technologies in Computing Systems, Vol. 3, No. 4, 2017.

M. Hassan Najafi, S Jamali-Zavareh, D. J. Lilja, M. Riedel, K. Bazargan, and R. Harjani, "Time-Encoded Values for Highly Efficient Stochastic Circuits," IEEE Transaction on Very Large Scale Integration Systems, Vol. 25, No 5, 2017.

Zhiheng Wang, Ryan Goh, Kia Bazargan, Arnd Scheel, and Naman Saraf, "Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map" , in IEEE Transactions on VLSI (TVLSI), 2016.

Divya Mahajan, Kartik Ramkrishnan, Rudra Jariwala, Amir Yazdanbakhsh, Jongse Park, Bradley Thwaites, Anandhavel Nagendrakumar, Abbas Rahimi, Hadi Esmaeilzadeh, Kia Bazargan, "AXILOG: Abstractions for Approximate Hardware Design and Reuse" , in IEEE Micro, Vol 35, No 5, pp. 16-30, 2015.