Ph.D. Electrical Engineering, 1992, University of Illinois, Urbana-Champaign, IL, United States
M.S. Computer Engineering, 1989, Syracuse University, Syracuse, NY, United States
B.Tech. Electrical Engineering, 1987, Indian Institute of Technology, Bombay, India
Computer-aided design of VLSI circuits and systems
My research is primarily in the area of computer-aided design (CAD) of VLSI systems. Advances in integrated circuit technologies allow us to build progressively larger systems, with increasing numbers of transistors. On the other hand, circuit components, such as transistors and wires, shrink in size from one technology generation to the next. Under such a scenario, CAD techniques are essential, both to model physical effects at the nanoscale and to solve large-scale problems with large numbers of variables. The research in our group is centered around design automation for optimization and analysis, concentrating on timing, power and layout issues. Some specific problems that we have worked on in the recent past include thermal analysis, reliability, power grid analysis, and 3D integration. Our focus has been on being able to build practical algorithms that can provide accurate solutions with a reasonable amount of computation.
Robert and Marjorie Henle Chair
2016 ACM Fellow for contributions to the enhancement of performance and reliability in integrated circuits
2014 Semiconductor Industry Association (SIA) University Research Award
2013, 2016 ICCAD Ten-Year Retrospective Most Influential Paper Award
Distinguished McKnight University Professor
2003 SRC Technical Excellence Award
2003 IEEE Fellow for contributions to the optimization of timing and layout in VLSI circuits
1995 NSF CAREER Award
Z. Liang and S. S. Sapatnekar, “Energy/Delay Tradeoffs in All-Spin Logic Circuits,” in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 2, no. , pp. 10-19, Dec. 2016.
M. G. Mankalale, and S. S. Sapatnekar, “Optimized Standard Cells for All-Spin Logic.” ACM Journal on Emerging Technologies in Computing Systems (JETC) 13, no. 2 (2016): 21.
F. S. Snigdha, D. Sengupta, J. Hu and S. S. Sapatnekar, “Optimal Design of JPEG Hardware under the Approximate Computing Paradigm,” 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, 2016.
D. Sengupta and S. S. Sapatnekar, “FEMTO: Fast error analysis in Multipliers through Topological Traversal,” 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, 2015, pp. 294-299.
V. Mishra and S. S. Sapatnekar, “The impact of electromigration in copper interconnects on power grid integrity,” 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, 2013.
Y. Zhan, S. V. Kumar, and S. S. Sapatnekar, “Thermally-Aware Design,” Foundations and Trends in Electronic Design Automation”, 2008.
C. J. Alpert, D. P. Mehta, and S. S. Sapatnekar, editors, Handbook of Algorithms for Physical Design Automation, CRC Press, New York, NY, 2008.
B. A. Goplen and S. S. Sapatnekar, “Placement of 3D ICs with Thermal and Interlayer Via Considerations”, Proceedings of the ACM/IEEE Design Automation Conference, pp. 626 – 631, 2007.
S. S. Sapatnekar, Timing, Kluwer Academic Publishers, Boston, MA, 2004
H. Chang and S.S. Saptnekar, “Statistical Timing Analysis Considering Spatial Correlations Using a Single PERT-like Traversal,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp.621-625, 2003.