Events Listing

Tau mislocalization to dendritic spines is a common mechanism in neurodegenerative diseases including AD and PD

Progressively more research suggests that diverse neurodegenerative diseases including Alzheimer’s disease (AD) and Parkinson’s disease (PD) share common pathological hallmarks and cellular mechanisms. One such mechanism involves the redistribution of microtubule associated protein tau (MAPT) from the axon into the somatodendritic compartments of neurons, leading to loss of tau polarity. Under normal physiological conditions, the distribution of tau proteins is polar. Tau is enriched in axons and has low presence in postsynaptic structures including the soma, dendrites and dendritic spines. In our recent studies, we found that the tau polarity is lost or reversed in neurodegenerative diseases. The loss of polarity is followed by mislocalization of tau into dendritic spines, the postsynaptic structures found in most excitatory glutamatergic synapses, and subsequent postsynaptic deficits and cognitive impairments. The clarification of the signaling steps that lead to tau-mediated synaptic deficits and cognitive impairments will shed new mechanistic insight on the pathogenesis of AD and PD. It may also uncover novel drug targets for treating and preventing these diseases. The combination of live imaging technique and spintronic technology will allow us to longitudinally monitor tau trafficking and electrophysiological activities at multiple time points and will be a powerful tool for mechanistic studies of tau mislocalization.

Professor Dezhi Liao is with the Department of Neuroscience at the University of Minnesota

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Driving Automotive ICs into Advanced CMOS

Automotive processors have become a multi-billion dollar market with ever growing demand for advanced silicon. Cars today are increasingly featured with better safety/autonomy, electrification, and connectivity. In this talk, we will cover how automotive electronics is evolving towards domain and zonal topologies to integrate more functionality, and provide a brief overview of NXP's portfolio to enable this evolution. We will discuss the opportunities and challenges that accompany the migration of these very cost-sensitive products to advanced CMOS nodes incorporating the fully depleted finFET. We will also summarize the key process technology elements that have enabled the advanced finFET CMOS nodes, highlighting the resulting device technology characteristics and challenges impacting design.

About Alvin Loke

Alvin Loke is a Fellow at NXP Semiconductors in San Diego. He has worked on CMOS nodes from 250nm to 2nm. A PhDEE graduate from Stanford, he spent several years in CMOS process integration and since 2001 has worked on analog/mixed-signal design focusing on a variety of wireline links, design/model/technology interface, and design methodologies. Alvin has been an active IEEE Solid-State Circuits Society (SSCS) volunteer since 2003, having served in roles including Distinguished Lecturer, AdCom member, CICC Committee Member, Webinar Chair, and JSSC/SSCL Guest Editor. He currently serves in the VLSI Symposium committee and as SSCS Chapters Chair. Alvin has authored over 60 publications including the CICC 2018 Best Paper and invited short courses at ISSCC, VLSI Symposium, and BCICTS. He holds 29 US patents.

International students: Are you wondering how to get started with the OPT or CPT request process? ISSS is here to help! This workshop will help get you ready to submit your OPT or CPT requests through MyISSS. The session will have a short presentation with information about the application process followed by time for questions.

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Technically Speaking is a free lively series of discussions that explores the intersection of technology and business. Each of our speakers plays a leadership role in the tech sector: they share their career journeys, what they've learned along the way, and how they believe new innovation will reshape their industries. Networking time before and after the talk as well as an extended Q&A makes this a unique and dynamic opportunity for technology students who want to learn more about the business of tech.

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Distributed synthesis for local controllers in networked systems

In traditional decentralized and distributed control, the subsystem level controllers are constrained to use states from a subset of neighboring subsystems to determine their control actions; however, the process of designing the controllers is centralized and utilizes the knowledge of the dynamics of all subsystems. For large scale systems involving plug and play operations, a distributed synthesis process in which the control synthesis is carried out locally at the subsystem level, without explicit knowledge of the dynamics of other subsystems in the network, may be required. We provide such a control design. We begin with a model based design and then extend it to consider the case when accurate models may not be available and a data-driven design is preferable.

About Professor Vijay Gupta

Vijay Gupta is the Elmore Professor of Electrical and Computer Engineering at Purdue University. He received his B. Tech degree at Indian Institute of Technology, Delhi, and his M.S. and Ph.D. at California Institute of Technology, all in Electrical Engineering. He received the 2018 Antonio Ruberti Award from IEEE Control Systems Society, the 2013 Donald P. Eckman Award from the American Automatic Control Council and a 2009 National Science Foundation (NSF) CAREER Award. His research and teaching interests are broadly in distributed decision making.

Professor Wei Yu of University of Toronto speaks on Active Learning for Communication and Sensing

The seminar can be attended in person or remotely via Zoom

Novel 2D Dirac and Weyl Semimetals

The discovery of graphene has stimulated enormous interest in two-dimensional (2D) electron gas with linear band structure. 2D Dirac materials possess many intriguing physical properties such as high carrier mobility and zero-energy Landau level for the relativistic dispersion and chiral spin/pseudospin texture. In this talk, we will discuss three new variants of 2D Dirac materials including (1) unpinned 2D Dirac semimetals in α-antimonene, (2) Rashba spin-split 2D Weyl semimetals in α-bismuthene, and (3) interacting Dirac states in graphene heterostructures4. The results offer new insights to the relativistic behavior of electrons in reduced dimensions. We will review the emergent properties and device applications of relativistic electrons in those 2D Dirac/Weyl semimetals, especially, cloning of Dirac fermions, Moiré flat bands, and spin/valley separators.

About Professor Guang Bian

Guang Bian is an associate professor at the department of physics and astronomy, University of Missouri, Columbia. Dr. Bian graduated with Phd degree from University of Illinois at Urbana in 2013, and performed postdoc research at Princeton University from 2013 to 2016. Dr. Bian has extensive experience in molecular beam epitaxy (MBE) fabrication and spectroscopic characterization of low-dimensional quantum systems and novel topological/functional materials. Dr. Bian’s research work has been recognized by “President's Early Career Award”, University of Missouri (2019), “Aladdin Lamp Award”, Synchrotron Radiation Center, Wisconsin (2010), and “Highly Cited Researcher” (2019-2022) by Clarivate Analytics. Dr. Bian has published 114 papers on quantum materials in peer-reviewed journals with >16,000 citations and h-index of 48 according to Google Scholar.

The talk has been moved to fall 2024

Error Resilient Neuromorphic Systems Using Embedded Predictive Neuron Checks

The reliability of emerging neuromorphic compute fabrics is of great concern due to their widespread use in critical data-intensive applications. Ensuring such reliability is difficult due to the intensity of underlying computations (billions of parameters), errors induced by low power operation and the complex relationship between errors in computations and their effect on network performance accuracy. In this talk, we study the problem of designing error-resilient neuromorphic systems where errors can stem from: (a) soft errors in computation of matrix-vector multiplications and neuron activations, (b) malicious trojan and adversarial security attacks and (c) effects of manufacturing process variations on analog crossbar arrays that can affect DNN accuracy. The core principle of error detection relies on embedded predictive neuron checks using invariants derived from the statistics of nominal neuron activation patterns of hidden layers of a neural network. Algorithmic encodings of hidden neuron function are also used to derive invariants for checking. A key contribution is designing checks that are robust to the inherent nonlinearity of neuron computations with minimal impact on error detection coverage. Once errors are detected, they are corrected using probabilistic methods due to the difficulties involved in exact error diagnosis in such complex systems. The technique is scalable across soft errors as well as a range of security attacks. The effects of manufacturing process variations are handled through the use of compact tests from which DNN performance can be assessed using learning techniques. Experimental results on a variety of neuromorphic test systems: DNNs, spiking networks and hyperdimensional computing are presented.

About Professor Abhijit Chatterjee

Abhijit Chatterjee is a Professor in the School of Electrical and Computer Engineering at Georgia Tech and a Fellow of the IEEE. He received his Ph.D. in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1990. Chatterjee received the NSF Research Initiation Award in 1993 and the NSF CAREER Award in 1995. He has received seven Best Paper Awards and three Best Paper Award nominations. His work on self-healing chips was featured as one of General Electric’s key technical achievements in 1992 and was cited by the Wall Street Journal. In 1995, he was named a Collaborating Partner in NASA’s New  Millennium project. In 1996, he received the Outstanding Faculty for Research Award from the Georgia Tech Packaging Research Center, and in 2000, he received the Outstanding Faculty for Technology Transfer Award, also given by the Packaging Research Center. In 2007, his group received the Margarida Jacome Award for work on VIZOR: Virtually Zero Margin Adaptive RF from the Berkeley Gigascale Research Center (GSRC). Dr. Chatterjee has authored over 450 papers in refereed journals and meetings, has 22 patents and supervised over 50 Ph.D dissertations. He is a co-founder of Ardext Technologies Inc., a mixed-signal test solutions company and served as chairman and chief scientist from 2000-2002. His research interests include error-resilient machine learning, signal processing and control systems, mixed-signal/RF/multi-GHz design and test and adaptive real-time systems.

Registration is required to attend the event

Join this session to prepare for the upcoming career fairs! This virtual event will feature helpful tips and information from presenters from ISSS and Career Services. All UMN international students who are attending spring career fairs are welcome to attend (including UMN system campuses). A recording will be made available. You must register via Zoom to receive the link to join. There will be two sessions of this workshop offered within the month of February 3 and February 21. We encourage you to attend one of the sessions.

Registration links for the events:

Friday, February 3, 12pm-1pm CT 
Zoom Registration 

Tuesday, February 21, 4pm-5pm CT 
Zoom Registration 

Please email UMN International Career Consultant, Jane, with any questions about this session at sitt0036@umn.edu.

Culture Corps Career STAR is a 6 session career skill development workshop series for undergraduate international students, beginning February 17th. This program is designed to help develop the necessary skills needed to obtain internships, jobs after graduation, and plan for graduate school. NEW this year, we are piloting a program partnership between UMN, Global Minnesota, and University of St. Thomas. Expand your network and development through this program where you can connect and learn with international student peers, professionals in the community, and international alumni who have graduated.

The Career STAR Program meets virtually via Zoom, on 6 Fridays from 11am-12pm CT. To achieve completion of the program we expect you will attend at least 4 out of 6 sessions.

Limited spots are available! Learn more and apply

UMN International Student Peer Leaders who have previously completed the Career STAR Program contribute to the leadership and facilitation of the program, thanks to support from UMN ISSS Culture Corps.

Email Jane, UMN International Career Consultant, with any questions about the program: sitt0036@umn.edu